Embodiments of the present invention relate to flash electrically erasable programmable read only memory semiconductor devices. More particularly, embodiments of the present invention provide a method and apparatus for partial page programming of a multi level flash device.
Flash memory is a type of semi conductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. However, flash memory generally can not be written to, or programmed, at rates comparable to random access memory, RAM. Further, flash generally must be erased, either in its entirety or in large segments called pages, prior to changing its contents.
Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example xe2x80x9cMP3xe2x80x9d players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
As discussed above, a page of flash memory generally must be erased before new data may be stored in that page. Erasing a page is generally a long process, typically measured in hundreds of milliseconds. This is a disadvantage compared to RAM and hard drives, which may be written directly, without an interposing erasure.
In order to mitigate this drawback, some flash devices are capable of partial page programming. Partial page programming is a technique whereby some of the contents of a page of flash memory may be updated without erasing. Typically, a cell of flash memory is described as being either in the erased state or the programmed state. Either state, programmed or erased, may be assigned the binary value 0, and the other state may be assigned the binary value 1.
Assuming the erased state is assigned the binary value 1, partial page programming generally allows instances of 1 in the programmed page to be changed to a value of 0, without an intervening erase process. In general, cells programmed to a value of 0 may not be changed to a 1 value. Changing a cell from a 0 to a 1 typically requires the page or block erase process.
The applications described above, and others, have driven very large demand for flash devices, both in total numbers of devices and in total bits. An innovative technique recently developed by several flash manufacturers is to store multiple bits in each cell of the flash device. For example, if the circuitry of a flash device could discern three storage levels for each cell, every two cells could store three bits of information, resulting in 50% more storage for the same memory cell area. If the cells could store four levels, the result would be to double the density of the device. This technique and capability is generally referred to as a multi level cell, or MLC.
Due to the high order density increases afforded by MLC, such designs are extremely attractive to both manufacturers and customers. Manufacturers benefit by being able to produce many more bits of flash memory without increased capital spending, and customers enjoy reduced physical product size and significant cost per bit advantages.
Unfortunately, partial page programming has not been available in conventional MLC devices, rendering MLC flash less attractive in many applications.
Therefore, what is needed is a method and apparatus for partial page programming of a multi level cell flash device. Partial page programming will bring many benefits to multi level cell flash devices.
Therefore, it would be advantageous to provide a method and system providing for partial page programming of multi level cell flash memory. A further need exists for a method of combining new information and previously stored information in a multi level flash memory device.
A method and apparatus for partial page programming of a multi level cell flash memory is disclosed. In a multi level cell flash memory, new partial page programming information may be accessed. Information previously stored in the memory may be accessed. New and previous information may be combined in a page buffer of a flash device. Optionally, new and previous information may be combined in a memory external to the flash device. The combined information may be used to program the cells of a flash memory. A standard programming and verification method may be used to program the combined information into the cells of a flash memory. In this novel manner the benefits of partial page programming may be realized for multi level cell flash memory devices.